The present invention relates to an asynchronous bus multiprocessor system with microinstructions being loaded from a working memory. Data processing systems are known where a plurality of processors each have a control memory intended to store microprograms, such microprocessors communicating with each other and with a working memory through a common bus. The working memory contains programs, data and microprograms. The control memory of each processor is actually comprised of two independent control memories; a read only memory and a read/write memory. Microprograms which reside in the working memory can be used after transfer of such microprograms in the control read/write memory. Such transfer is made by means of a microprogram resident in the control read only memory. An example of such architecture is described in U.S. Pat. No. 3,478,322. It is however restricted to the case of a monoprocessor system.
Microprogrammed systems are further known where the working memory is integral to the central unit and is synchronized with it. In such systems it is possible to read out and execute microinstructions contained in the working memory one at a time. An example of such system is disclosed in British Pat. No. 1,440,856. In these systems the use of the working memory as control memory and the interface problems in memory access are solved by the use of a so-called hardware sequencer which is activated for read out, and by executing a microinstruction resident in the working memory. Such sequencer, when activated, generates a series of microinstructions to control the system operation during several machine cycles, as necessary to read out from working memory the resident microinstruction and to execute such microinstruction in case it requires a read memory operation. Such systems are more efficient than the previously mentioned ones because only those microinstructions are transferred from the working memory which are actually needed, with a so-called "hot" reading and execution process; i.e., by individual request of microinstructions and related immediate execution. It is desirable that this type of solution be also applied to multiprocessor systems connected to each other and to a working memory via a common bus in order to obtain the same advantages. However the adoption of such solution to multiprocessor systems presents great difficulties and there are no examples in the art of which the applicants are aware. In bus multiprocessor systems the bus is shared by the several processors in different time slots. Additionally the operation of each processor is carried out in a completely asynchronous way with respect to the other processors and the working memory. Each processor operates substantially on the basis of machine cycles, while the working memory and the bus operate on the basis of memory cycles which are related to a bus cycle. The processor cycles are neither synchronized to each other nor to the bus cycles. Moreover, processor cycles are generally shorter than bus and memory cycles.
A synchronization mechanism is therefore necessary to enable the interface between a processor and the memory through the bus and to prevent possible interferences among processors in communicating with memory. Such synchronization mechanism requires that each processor be provided with registers interfacing to the bus and with logic to hold the information which is to be exchanged with memory during the time necessary for synchronization and dialog. Therefore a memory access operation; e.g., a read operation, functionally requires three separate operations which are developed in at least two machine cycles and in one bus cycle. During a first machine cycle some commands and a memory address are arranged within the interface register. At the end of the cycle a bus access and a read memory request is set and the requesting processor must stop each activity and wait for the read out information. Therefore a wait-pause starts when the bus and memory control apparatus responds to the request with its own decisional criteria and with its own timing; this starts a dialog with the register and the interface logic of the processor. During this time the processor stays inactive. This involves at least a bus cycle development at the end of which the information read out from memory is loaded into an interface register of the processor and the processor can start again with its activity. At this point in a second machine cycle, the information contained in the interface register may be transferred to a working register for handling, if required. Accordingly the concept disclosed in the mentioned British patent if applied to a multiprocessor system would require three machine cycles and a bus cycle for the execution of a working memory resident microinstruction. In a first machine cycle the interface register loading occurs. In a bus cycle the memory access operation and the loading of the read out microinstruction into an interface register occur. In a second machine cycle a microinstruction register is loaded; whereas in a third machine cycle the microinstruction is executed. It is clear that such operations can only be carried out under control of a sequencer and it is also clear that the operation of the system takes place in a very slow way. A further reduction in speed is caused by the interference among operations of memory access, and read-out from memory of the microinstruction stored therein. Normally, in a microprogrammed processor, a microinstruction execution overlaps with the fetching of the subsequent microinstruction in one machine cycle. Such overlapping cannot take place when the executed microinstruction commands a memory access and the subsequent microinstruction is stored in the working memory. Accordingly the teaching of the subject British patent when applied to the execution of a memory access microinstruction and the fetching of the subsequent microinstruction from the working memory would require at least three machine cycles and two bus cycles as follows:
(1) machine cycle: loading of the interface registers with memory address and related read/write commands. PA1 bus cycles: read/write memory. PA1 (2) machine cycle: loading of interface registers with microinstruction address in working memory and related read command. PA1 bus cycle: read memory. PA1 (3) machine cycle: transferring of the microinstruction from interface register to microinstruction register.
A microinstruction execution cycle would then follow these cycles.